SIIG 4-Port RS232 Serial PCI with 16550 UART Uživatelský manuál

US7729/09AHardware Architecture Reference Platform User’s Manual US7729-HCB1/10/11 & US7709A-HCB1/10/11 US7729-HRP10A & US7709A-HRP10A US7729

8 Section 2 Quick Start Guide (WinCE) This section describes the following for the SH7709A/7729 HARP: • The hardware and software requirements.

9 2.1.3 Shipped with SH7709A/7729 HARP • SH7709A/7729 base board (Key West) with face plate • System I/O daughter board (Tahoe) with face plate •

10 * For reference, if the user would like to boot into the WinCE OS installed in FLASH, switch S1 would be set to: OFF OFF OFF OFF 2.2 Harp Connec

11 • Data bits: 8 • Parity: None • Stop bits: 1 • Flow control: None 5. File->Save. Save these settings so that you don’t have

12 4. The command prompt shell will appear on the display monitor. 5. Typing dir <Enter> will display a list of files and folders from Window

13

14 Section 3 Quick Start Guide (VxWorks) The following information gives guidelines and suggestions for the setup of the SH7751 HARP when using t

15 3.2 Download BSP from Platform Support Site 1. Using a standard web browser, view the following page: http://ftp.hsa.hitachi.com/netshare/c

16 3.4 Build VxWorks and Boot ROM Images 1. Make sure the Tornado Registry is running. You should see its icon in the Windows tray on the taskb

17 3.5 Downloading “bootrom.hex” Image to the Target There are several methods available to download images to the target. We will use DMON’s “LE”

Notice When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All

18 3.6 Setup FTP Server 1. Start the FTP server from the Start→→→→Programs→→→→Tornado2 menu. 2. Select “Users/rights…” from the “Security” menu t

19 Section 4 Hardware Description Functional Description CPU The Key West may be configured with either a Hitachi SH7709A or SH7729 SH3 process

20 Pushing this button has the exact same effect as an assertion of PRST# on the CPCI bus. The system is forced into a hard-reset state whenever thi

21 Table 2: Debug Serial Port Pin-out Pin Name Pin Name 1 DBG_CD 6 DBG_DSR 2 DBG_RX 7 DBG_RTS 3 DBG_TX 8 DBG_CTS 4 DBG_DTR 9 DBG_RI 5 GND T

22 Bus Speed Frequency SDRAM 66 MHz V3-PCI Bridge 66 MHz SMSC Ethernet 66 MHz I/O Expansion 66 MHz Timers The SH7709A/7729 and 64465 chips pro

23 • False start bit detection VGA Graphics The graphics controller supports the MediaQ MQ-200 companion chip. The controller provides up to 1280 x

24 configuration a special parallel port cable must be used. This cable can be obtained from Redmond Cable Corp., in Redmond, WA, PN MIC-64355913 (1

25 Table 6: IrDA connector Pin-out Pin Name Direction Function 1 TX I Transmit data 2 SEL1/ID1 I/O I/O Pin for identification 3 GND O Ground

26 Table 8 HARP LCD Header Signal Definitions Name Function DF The DF signal is used on some LCD panels for internal biasing. It is a clocking sig

27 43 P18 44 P19 45 GND 46 P21 47 P20 48 P23 49 P22 50 GND Table 10: LCD Data Format Data Pin Citizen Color K6488L-FF 640x480 scan-l

i Contents Section 1 Overview...

28 • Area 5 is allocated to PC Card Channel 1 (PCC1) and supports both memory and I/O interfaces. The ability to switch between Attribute memory or

29 Microsoft has a reference platform that is used for running Windows CE inside an automobile called Auto PC. It consists of a CPU and a support ca

30 Signal Name Definition CS3 Chip select for the 64 Mbytes of SDRAM RAS3L/PTJ0 RAS for lower 32 Mbytes SDRAM RAS3U/PTE2 RAS for upper 32 Mbytes

31 Section 5 Programmer’s Guide Memory Map The SH7729 Key West Demonstration Platform is a stand-alone computing system. The SH3 MCU supports up

32 0 0x0000 0000 0x03FF FFFF 000 64MB CS0 8 bit 32 bit Boot ROM (512k x 8) or Flash (1M x 32 bit) with boot from Flash 1 0x0400 0000 0x07FF FFFF

33 Table 13: HD64465 Address Mapping IrDA RegisterUART RegisterParallel Port RegisterTimer RegisterGPIO RegisterPCMCIA RegisterStandby & System

34 See the HP HDSP-2534 device specification for further details of this register space. All functional aspects of this display are supported. Speci

35 PCMCIAEN: A “1” indicates that the PCMCIA decode is enabled for CS5 & CS6 address space. A “0” indicates that the PCI aperture decode is enab

36 Debug Register Base Address: 0x11FF A000 Data Assignments (RO = Read-Only, RW = Read-Write): D07 D06 D05 D04 D03 D02 D01 D00 N/A DEBUG6 DEBUG

37 Table 14: MQ-200 Address Mapping 64464 RegisterSpaceFrame BufferReserved0x1200 0000-0x12FF FFFF0x1300 0000-0x13DF FFFF0x13E0 0000-0x13FF FFFF16MB

ii Bus Control Register 1 (BCR1) ...53 Bus Con

38 S1-2 DEBUSERIAL# 7709A/7729 PTG1; Rev 4 Bd. or less only S1-3 FLASHPROT# 7709A/7729 PTG2; Rev 4 Bd. or less only S1-4 MISCSW 7709A/7729 PTG3

39 Table 18: SDRAM 64MB tests Test Number Data Width Test/Data Written 1 32 bit Write Background of 0xFFFFFFFF and then walk through and read b

40 Compact PCI Interface The Compact PCI bus interface supports four standard bus interrupts A, B, C and D. Additionally we need to support two lega

41 Timers . The timer resources are in the 7709A/7729 and the HD64465 companion chip. Product RS-232 Port Table 23: Product Serial Port Resource As

42 PP_BUSY HD64465 BUSY PP_PE HD64465 PE PP_SLCT HD64465 SLCT PP_IPD[0..7] HD64465 PPD[0..7] PS/2 Mouse Port The PS/2 mouse support is

43 PC0WP HD64465 PCC0WP#/IOIS16# PC0RDY HD64465 PCC0RDY/IREQ0# PC0BVD1 HD64465 PCC0BVD1/STSCHG0# PC0BVD2 HD64465 PCC0BVD2/SPKR0 PC0CD1 HD6446

44 USB These signals connect to the two stacked USB connectors on the Tahoe board. Table 30: USB Resource Assignment Signal Source I/O Port Notes US

45 Table 32: Sound System Resource Assignment Signal Source I/O Port Notes AD_ACCLK HD64465 ACCLK AD_ACRST# HD64465 ACRST# AD_ACPD# HD64465 A

46 SENOUT6 HD64465 PA6 R/W SENOUT7 HD64465 PA7 R/W Smart Card Interface Table 36: Smart Card Port Assignment Signal Source I/O Port Notes SH_S

47 Four Wire Touch Screen Input Table 37: Four-Wire Touch Screen Resource Assignment Signal Source I/O Port Notes GPIO3 HD64465 PE2 Output GPIO2

iii Read Me First If you do nothing else please review sections 2 and 3 before you start. This will reduce the initial startup problems that may oc

48 TP HD64465 PE[4..7] I/O Test Point Definitions TP4 IRQOUT- 7709A/7729 TP1 PTC7/PINT7 7709A/7729 TP8 PTE7 7709A/7729 TP6 PTG4 7709A/7729

49 PINT10 AutoPC Interrupt conn. AUTOINT2 Low PINT11 AutoPC Interrupt conn. AUTOINT3 Low PINT12 AutoPC Interrupt conn. AUTOINT4 Low PINT13 Aut

50 RS-232 Ports SCIF Port Definition RXD1/SCPT2 DTR (software controlled) SCK1/SCPT3 CD (software controlled) RxD2/SCPT4 Receive data (console,

51 Appendix A Key West Bill of Material (BOM) This will is listed on the CD that can be obtained after signing the Agreement included in the Shi

52 Appendix B Tahoe PCB Bill of Material (BOM) This is listed on the CD that can be obtained after signing the Agreement included in the Shipping

53 Appendix C SH7709A/7729 Registers The following is a detailed description of the SH3 registers used to initialize the processor at power-up/res

54 Wait State Control Register 1 (WCR1) Wait state control register 1 (WCR1) specifies the idle time between area changes and a read to a write in t

55 Individual Memory Control Register (MCR) The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS and CAS

56 Refresh Time Constant Register (RTCOR) Refresh time constant register (RTCOR) defines the period between each refresh cycle. It is calculated by

57 Appendix D Key West Jumpers (listed by Function) Following is a detailed description of the jumper locations on the Key West PCB. The jumpers a

4 Section 1 Overview 1.1 Introduction The Hitachi SuperH tm microprocessor-based Hardware Architecture Reference Platform (HARP) consists of a p

58 JP41 & JP42 Clock Skew Controls clock skew for: Sysclk, SDRAM Off-board clocks. CPLD Programming Port JP2 System CPLD (6 p

59 PCI and PCMCIA J5 & J7 & J11 CompactPCI Connectors JP7 PCI Clock Frequency Select In = 16.6 MHz *Out = 33 MHz JP35 PCM

60 Appendix E Key West Jumpers (listed by Jumper number) Following is a list of the jumper locations on the Key West PCB. The jumpers are listed i

61 J5 CompactPCI Connector J6 VGA Connector (15 pin female) J7 CompactPCI Connector J8 USB Connector (4 pins) J9 Serial Debug (9 pin ma

62 Appendix F Tahoe Daughterboard Connectors External Connectors J1 Line In J2 Mono Mic In J3 Amplified headphone out J4A PS/2 Keyboard C

5 1.2 Key West Base Board Features Figure 1.1 SH7709A/7729 Base Board (Key West) • SH7709A/7729 processor running at 133 MHz (3.3 V) • Syste

6 1.3 Tahoe Daughter Board Features Figure 1.2 Tahoe I/O Board HD64465 • PCMCIA interface that supports PCMCIA Rev. 2.1/JEIDA version 4.2 (2

7 Figure 1.2 SH7709A/7729 HARP -- Key West + Tahoe